Modern electronics, such as smart phones, personal digital assistants, location based services devices, digital cameras, music players, servers, and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Both higher performance and lower power are also quintessential requirements for electronics to continue proliferation into everyday. For example, more functions are packed into a cellular phone with higher performance and longer battery life. Numerous technologies have been developed to meet these requirements.
Integrated circuits are often manufactured in and on silicon and other integrated circuit wafers. Integrated circuits include literally millions of metal oxide semiconductor field effect transistors (MOSFET). Advances in integrated circuit technology continue to shrink the sizes of these transistors and drive for higher performance with minimum power consumption. This dichotomy has inspired various approaches to solve the need for speed at lower power.
As fabrication techniques for semiconductor integrated circuits have developed, the number of elements in a chip has increased. Element size has decreased as integration density has increased. Fabrication line width has decreased from sub-micron to quarter-micron, and smaller. Regardless of the reduction in element size, however, adequate insulation or isolation must be required among individual elements in a chip so that optimal performance can be achieved. The main object is to form isolations among individual elements, reducing their size as much as possible and ensuring superior isolation while creating more chip space for more elements.
Among the different element isolation techniques, local oxidation of silicon (LOCOS) and trench isolation are the most common. The trench isolation technique has received particular notice as it provides a small isolation region and the substrate surface remains level post process. The conventional deposition method for fabricating trench isolations with high aspect ratio requires multiple deposition and etching cycles, thus it is expensive and offers reduced yield. Additionally, as the density of integrated circuits increases and element size is reduced, the deposition method provides inadequate step coverage resulting in incompletely filled trenches, resulting in detrimental isolation and further reduced yields.
As the aspect ratio of the trenches increase to keep up with the increasing density of integrated circuits, the trench process suffers from gap fill issues. In order to avoid gap fill issues, the trench process has become more complicated, such as multiple deposition and sputter/etch steps, and the manufacturing cost has increased. The aspect ratio may also decrease the distance the carrier has to travel to cause isolation failure resulting in increasing failures. The distance may also be further reduced, if isolation structures are misaligned with respect to the circuits they are to protect. The increasing density and higher aspect ratio result in integrated circuits that are more sensitive to isolation variations such as gap fill and misalignment.
As the demand for smaller electronic devices grows, manufacturers are seeking ways to increase density of the elements in the integrated circuit while providing isolation technology and at the same time, reducing manufacturing complexity, costs and failures. Prior attempts to increase density while providing isolation have brought additional fabrication cycles, additional costs, reduced performance, and reduced yields.
Thus, a need still remains for improving the yield, cost, and size of the basic transistor structures and manufacturing to obtain maximum performance improvement, power reduction, or both. In view of the demand for faster microprocessors and memory devices, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.